1. Field of the Invention
The present invention relates to a driving circuit for an active matrix type flat display device. More particularly, the present invention relates to a driving circuit for a liquid crystal display device which realizes gray-level display with 256 or more gray levels.
2. Description of the Related Art
FIG. 17 shows a configuration of a conventional driving circuit corresponding to one output of a 3-bit digital driver.
The driving circuit of FIG. 17 includes a sampling memory 131, a hold memory 132, and an output circuit 133. In response to a rising edge of a sampling pulse T.sub.smp, 3-bit digital data D.sub.0 to D.sub.2 are stored in the sampling memory 131. The digital data stored in the sampling memory 131 are then transferred in response to a rising edge of an output pulse OP to the hold memory 132 to be held therein. The output circuit 133 outputs one of gray level voltages V.sub.0 to V.sub.7 supplied externally in accordance with the values of the digital data held in the hold memory 132 as an output voltage Out.
FIG. 18 shows a configuration of the output circuit 133 which includes a 3-to-8 decoder 141 and eight analog switches ASW.sub.0 to ASW.sub.7. The decoder 141 turns on one of the analog switches ASW.sub.0 to ASW.sub.7 in accordance with the values of the digital data. A gray level voltage supplied to the turned-on analog switch is output as the output voltage Out.
A digital driver having the configuration shown in FIGS. 17 and 18 has advantages of simple structure and small power consumption and thus has been widely used. Such a digital driver is described, for example, in H. Okada et al., "Development of a low voltage source driver for large TFT-LCD system for computer applications", 1991, International Display Research Conference, pp. 111-114.
The conventional digital driver having the above configuration requires the same number of gray level sources as the number of gray levels to be displayed. This causes no problem for a 3-bit digital driver, but may cause a problem when a digital driver is driven with more than 3 bits because the number of required gray level sources becomes too large. Specifically, it is practically impossible to realize a 6 or more bit digital driver with the above configuration to provide a display with a large number of gray levels.
To overcome the above problem, various techniques have been proposed for realizing a display with a large number of gray levels by generating interpolation voltages between gray level voltages supplied externally.
One example of such techniques is disclosed in Japanese Laid-Open Patent Publication No. 5-273520, which describes a circuit for generating interpolation voltages between adjacent gray level voltages by dividing the gray level voltages by use of resistances in a driver. Hereinbelow, this technique of generating interpolation voltages by use of resistance is referred to as a "resistance division technique".
FIG. 19 shows a driving circuit 151 and a voltage dividing circuit 152 described in Japanese Laid-Open Patent Publication No. 5-273520 mentioned above. The driving circuit 151 corresponds to one output of a 4-bit digital driver.
The voltage dividing circuit 152 divides five external gray level voltages V.sub.0, V.sub.4, V.sub.8, V.sub.12, and V.sub.15 by use of resistances to generate one or more interpolation voltages between every two adjacent gray level voltages. As a result, total 16 voltages V.sub.0 to V.sub.15 composed of the five gray level voltages and 11 interpolation voltages are supplied to the driving circuit 151.
The driving circuit 151 selects one of the 16 voltages V.sub.0 to V.sub.15 supplied from the voltage dividing circuit 152, and outputs the selected voltage via a buffer amplifier 157.
Referring to FIGS. 20A, 20B, 21, and 22, an application of the technique disclosed in Japanese Laid-Open Patent Publication No. 5-273520 mentioned above to a 6-bit digital driver will be described.
FIG. 20A shows a configuration of a voltage dividing circuit 162, which divides nine external gray level voltages V.sub.0, V.sub.8, V.sub.16, V.sub.24, V.sub.32, V.sub.40, V.sub.48, V.sub.56, and V.sub.64 by use of resistances to generate seven interpolation voltages between every adjacent gray level voltages. As a result, 64 total voltages V.sub.0 to V.sub.63 composed of eight gray level voltages and 56 interpolation voltages are supplied to a driving circuit 161.
FIG. 20B shows an array of eight resistances connected in series between the gray level voltages V.sub.0 and V.sub.8 shown in FIG. 20A. Such an array of eight resistances is also provided between any of the other adjacent gray level voltages.
FIG. 21 shows a configuration of the driving circuit 161 which corresponds to one output of the 6-bit digital driver.
FIG. 22 shows a configuration of an output circuit 173 of the driving circuit 161 of FIG. 21. The output circuit 173 includes a 6-to-64 decoder 181 and 64 analog switches ASW.sub.0 to ASW.sub.63. The 64 voltages V.sub.0 to V.sub.63 output from the voltage dividing circuit 162 are supplied to the analog switches ASW.sub.0 to ASW.sub.63, respectively. The decoder 181 turns on one of the analog switches ASW.sub.0 to ASW.sub.63 in accordance with the value of digital data. A voltage supplied to the turned-on analog switch is output via a buffer amplifier 183 as an output voltage Out.
An "oscillating voltage technique" is also known as a technique for realizing a display with a large number of gray levels by generating interpolation voltages between gray level voltages supplied externally. The oscillating voltage technique is based on a principle completely different from that of the resistance division technique described above. The principle of the oscillating voltage technique will be described.
It is generally known that a periodic function can be expanded to a Fourier series as long as it can be integrated. Therefore, a voltage which oscillates between a voltage v.sub.i and a voltage v.sub.j at a duty ratio of m:n as shown in FIG. 23 is represented by Expression (1) below as a function f(t). ##EQU1##
The first term of the function f(t) represents a DC component shown as an average voltage and the second term thereof represents a periodic component. If the periodic component of the function f(t) can be removed somehow, a pixel electrode which receives an oscillating voltage as shown in FIG. 23 from a driver has an effect substantially equivalent to that the pixel electrode may have when it receives only a DC component represented by the first term of the function f(t).
If the route extending from a data line to a pixel electrode via a TFT is considered as a load of a driver, the route has characteristics as a low-pass filter determined based on a resistance component and a capacitance component existing on the route. If the frequency of the oscillating voltage is set sufficiently higher than a cut-off frequency determined by the characteristics as the low-pass filter, the value of the second term of the function f(t) can be sufficiently suppressed. As a result, a DC voltage shown as an average voltage is applied to the pixel electrode. Thus, in the oscillating voltage technique, a periodic component of an oscillating voltage output to a data line is suppressed using the characteristics of the route extending from the data line to the pixel electrode as the low-pass filter, so that only the DC component of the oscillating voltage is applied to the pixel electrode.
FIG. 24A shows a configuration of a circuit which corresponds to one output of a 6-bit digital driver according to the oscillating voltage technique. The circuit receives nine gray level voltages supplied externally and four interpolation signals t.sub.1 to t.sub.4 generated inside the driver. As shown in FIG. 24B, the interpolation signals t.sub.1 to t.sub.4 have duty ratios of 7:1, 6:2, 5:3, and 4:4, respectively.
A logic circuit 191 selects two adjacent gray level voltages from the nine gray level voltages based on the values of the three most significant bits D.sub.5 to D.sub.3 of digital data. The logic circuit 191 also selects one of total eight signals, i.e., a signal having a duty ratio of 8:0, the signals t.sub.1 to t.sub.4, and signals t.sub.1 bar to t.sub.3 bar obtained by inverting the signals t.sub.1 to t.sub.3, based on the values of the three least significant bits D.sub.2 to D.sub.0. The duty ratios of the eight signals are 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, 1:7, respectively. As a result, an oscillating voltage which oscillates between the two gray level voltages selected based on the values of the three most significant bits at a duty ratio selected based on the values of the three least significant bits is obtained, and output to a data line connected to a pixel electrode. See Japanese Patent Publication No. 7-7248 (U.S. Pat. No. 5,583,531) for details of the oscillating voltage technique.
A 6-bit digital driver realizing 64 gray levels can be obtained without so much difficulty by the above-described conventional techniques. However, it is very difficult to obtain an 8-bit digital driver realizing more than 64 gray levels, e.g., 256 gray levels.
FIG. 25A shows a configuration of a voltage dividing circuit 192 for an 8-bit digital driver according to the resistance division technique. FIG. 25B shows a resistance array between gray level voltages V.sub.0 and V.sub.32 shown in FIG. 25A. Such a resistance array is also provided between any of the other adjacent gray level voltages.
According to the resistance division technique, the voltage dividing circuit 162 for the 6-bit digital driver needs 64 resistances as shown in FIGS. 20A and 20B since eight resistances are required between every two adjacent gray level voltages. For the 8-bit digital driver, the voltage dividing circuit 192 needs 256 resistances since 32 resistances are required between every two adjacent gray level voltages.
The 8-bit digital driver thus requires four times as many resistances as the 6-bit digital driver. This increases the area occupied by the voltage dividing circuit. Moreover, it is not easy to form a number of resistances in an LSI with high precision. If the values of the resistances vary, the resultant voltages obtained by the division deviate.
In the 6-bit digital driver, 64 voltages V.sub.0 to V.sub.63 are supplied from the voltage dividing circuit 162 to the driving circuit 161. In the 8-bit digital driver, 256 voltages V.sub.0 to V.sub.255 are supplied from the voltage dividing circuit 192 to a driving circuit.
Voltages output from the voltage dividing circuit are supplied to the driving circuit via voltage supply lines. Therefore, the 8-bit digital driver requires four times as many voltage supply lines as the 6-bit digital driver. This increases the area occupied by the voltage supply lines of the 8-bit digital driver by four times, resulting in increasing the chip area.
FIG. 26 shows a configuration of an output circuit 203 of the driving circuit of the 8-bit digital driver according to the resistance division technique.
An 8-to-256 decoder 211 of the output circuit 203 of the 8-bit digital driver requires a considerably large number of logic gates compared with the 6-to-64 decoder 181 of the output circuit 173 of the 6-bit digital driver. Also, the output circuit 203 of the 8-bit digital driver requires four times as many analog switches as the output circuit 173 of the 6-bit digital driver. The output circuit 203 of the 8-bit digital driver therefore becomes considerably large compared with the output circuit 173 of the 6-bit digital driver.
The decoder is not necessarily composed of a combination of logic gates. For example, the decoder may be composed of read-only memories (ROMs). Using ROMs, however, the 8-to-256 decoder 211 still becomes considerably large compared with the 6-to-64 decoder 181.
One driver includes the same number of output circuits as the number of drive terminals. As the size of the output circuit increases, therefore, the size of an LSI constituting the driver considerably increases.
For example, assume that a driver has 240 drive terminals. When the size of one output circuit corresponds to 50 gates, the size of the entire driver corresponds to 12000 (=50.times.240) gates. When the size of one output circuit corresponds to 100 gates, the size of the entire driver corresponds to 24000 (=100.times.240) gates. Thus, though one driving circuit only has additional 50 gates, as many as 12000 gates are added in the entire driver.
Due to the above-described reasons, it is considerably difficult to realize an 8-bit digital driver by the mere extension of the conventional resistance division technique.
FIG. 27 shows a configuration of a circuit which corresponds to one output of an 8-bit digital driver according to the oscillating voltage technique. oscillating signals t.sub.1 to t.sub.16 have duty ratios of 31:1, 30:2, 29:3, 28:4, 27:5, 26:6, 25:7, 24:8, 23:9, 22:10, 21:11, 20:12, 19:13, 18:14, 17:15, and 16:16, respectively.
A logic circuit 253 selects two adjacent gray level voltages from nine gray level voltages V.sub.32i (i=0, 1, 2, . . . , 8) based on the values of the three most significant bits D.sub.7 to D.sub.5 of digital data. The logic circuit 253 also selects one of 32 signals including a signal having a duty ratio of 32:0 based on the values of the five least significant bits of the digital data, as in the case of the 6-bit digital driver. As a result, an oscillating voltage which oscillates between the selected two gray level voltages at a duty ratio of a selected signal is output.
As described above, the 8-bit digital driver according to the oscillating voltage technique appears to be more practical than the 8-bit digital driver according to the resistance division technique. Nonetheless, the logic circuit 253 of the 8-bit digital driver becomes considerably large compared with the logic circuit of the 6-bit digital driver. This increases the chip size of the resultant LSI.
Another problem is that as the number of bits increases the minimum pulse width of the oscillating signal becomes significantly small. For example, consider two cases where a potential difference is equally divided into eight and where the same potential difference is equally divided into 32 for an oscillating voltage with the same frequency. The minimum pulse width obtained when the potential difference is divided into 32 is only a quarter of that obtained when it is divided into eight.
FIG. 28A shows a waveform of a signal having the minimum pulse width in the 6-bit digital driver. FIG. 28B shows a waveform of a signal having the minimum pulse width in the 8-bit digital driver. The output circuit of a driver needs to be designed to be operable for the minimum pulse width. This means that analog switches of the output circuit of the 8-bit digital driver where the minimum pulse width is a quarter of that in the 6-bit digital driver need to be designed to be operable at a speed, i.e., a frequency, substantially four times as high as those of the 6-bit digital driver. Hereinbelow, such a frequency is referred to as a "substantial frequency".
It would be understood that, if the frequency of an oscillating signal used in the 8-bit digital driver is reduced to a quarter of that used in the 6-bit digital driver, the minimum pulse widths of the two digital drivers becomes the same. Therefore, in this case, the same substantial frequency as that for the 6-bit digital driver may be used for the 8-bit digital driver.
However, as described in Japanese Patent Publication No. 7-7248 (U.S. Pat. No. 5,583,531) mentioned above, the frequency of an oscillating signal is an important factor for determining the deviation of a voltage to be applied to a pixel electrode. In order to unify the deviation of the voltage, reducing the frequency of the oscillating signal is not allowed. Moreover, the deviation of the voltage allowable for the 8-bit digital driver should preferably be smaller than that allowable for the 6-bit digital driver. To achieve this, the frequency of an oscillating signal used in the 8-bit digital driver needs to be higher than that used in the 6-bit digital driver.
When the frequency of the oscillating signal used in the 8-bit digital driver is the same as that used in the 6-bit digital driver, the substantial frequency for the former is four times that for the latter. If the frequency of the oscillating signal used in the 8-bit digital driver is made twice that used in the 6-bit digital driver to reduce the deviation of the voltage applied to a pixel electrode, the substantial frequency for the former becomes eight times that for the latter.
The substantial frequency can be increased by increasing the current capacity of the analog switches of the output circuit. An analog switch with a larger current capacity turns on more swiftly for a same capacitive load. This results in increasing the substantial frequency.
In order to increase the current capacity of an analog switch, however, the width of a transistor constituting the analog switch should be increased. This greatly affects the chip size. More specifically, one analog switch is generally composed of four MOS transistors. One output circuit includes a plurality of analog switches. One driver includes a number of output circuits. An increase of the size of one analog switch therefore greatly increases the size of the entire driver.
As the size of the gate of an MOS transistor increases, the capacity of the gate increases. The increase in the gate capacity causes an increase in power consumed when the analog switch is switched because power consumption is proportional to the capacity. As a result, the power consumption of the entire driver increases.
A factor which increases the power consumption of the entire driver more significantly than the gate capacity is a current flowing through the CMOS analog switch when the analog switch is switched, i.e., a through current. The through current increases in proportion to the increase of the gate width. This increase of the through current also increases the power consumption of the entire driver.
For the reasons described above, although the 8-bit digital driver according to the oscillating voltage technique is practicable, many restrictions still exist for the designing of an idealistic driver in the aspects of the chip size and power consumption. These restrictions also block the fabrication of a display device driven with such a driver.
The 8-bit digital driver according to the oscillating voltage technique is described in H. Okada et al., "An 8-bit digital data driver for AM LCDs", SID'94 Digest, pp. 347-350, for example.
Thus, to summarize the above, an 8 or more bit digital driver cannot be realized by the conventional resistance division technique. An 8-bit digital driver according to the conventional oscillating voltage technique can be realized and has already been realized.
However, increasing the substantial frequency for the 8-bit digital driver is limited because it increases the chip size and power consumption. As a result, the fabrication of a liquid crystal display device driven with such a driver is restricted.
An objective of the present invention is to provide a digital driver where advantages of the resistance division technique and the oscillating voltage technique are utilized, while shortcomings of these techniques are suppressed.
Specifically, an objective of the present invention is to realize not only an 8-bit digital driver realizing 256 gray levels, but also a 10-bit digital driver realizing 1024 gray levels which is considered impossible by conventional techniques.
Since human eyes are believed to have a resolution of about 1000 gray levels, it is meaningless to provide a resolution of more than 1000 gray levels. The 10-bit digital driver realizing 1024 gray levels is therefore an ultimate driver.